The present invention relates to photolithography techniques, and, more particularly, relates to improved methods and apparatuses for performing optical proximity correction techniques to minimize to occurrence of electromigration in conductive lines in the metallization layers caused by topographical variances.
The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography.
Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers (e.g., regions of substrate, polysilicon, or dielectric).
An integral component of photolithographic apparatus is a "reticle" which includes a pattern corresponding to features at a layer in an IC design. Such reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a "stepper" apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (regions not having chromium patterns) and projects onto the resist covered silicon wafer. In this manner, an image of the reticle is transferred to the resist.
The resist (sometimes referred to as a "photoresist") is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface. The resist material is classified as either positive or negative depending on how it responds to light radiation. Positive resist, when exposed to radiation becomes more soluble and is thus more easily removed in a development process. As a result, a developed positive resist contains a resist pattern corresponding to the dark regions on the reticle. Negative resist, in contrast, becomes less soluble when exposed to radiation. Consequently, a developed negative resist contains a pattern corresponding to the transparent regions of the reticle. For simplicity, the following discussion will describe only positive resists, but it should be understood that negative resists may be substituted therefor. For further information on IC fabrication and resist development methods, reference may be made to a book entitled Integrated Circuit Fabrication Technology by David J. Elliott, McGraw Hill, 1989.
One problem associated with photolithography is that light passing through a reticle is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process.
To remedy this problem, a reticle correction technique known as optical proximity correction ("OPC") has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion likely will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
FIGS. 1A through 1D will now be described to illustrate the OPC process. FIG. 1A shows a hypothetical reticle 100 corresponding to an IC layout pattern. For simplicity, the IC pattern consists of three rectangular design features. A clear reticle glass 110 allows radiation to project onto a resist covered silicon wafer. Three rectangular chromium regions 102, 104 and 106 on reticle glass 110 block radiation to generate an image corresponding to intended IC design features.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they can not be ignored in layouts having features smaller than about 1 micron.
FIG. 1B illustrates how diffraction and scattering affect an illumination pattern produced by radiation passing through reticle 100 and onto a section of silicon substrate 120. As shown, the illumination pattern contains an illuminated region 128 and three dark regions 122, 124, and 126 corresponding to chromium regions 102, 104, and 106 on reticle 100. The illuminated pattern exhibits considerable distortion, with dark regions 122, 124, and 126 having their corners rounded and their feature widths reduced. Other distortions commonly encountered in photolithography (and not illustrated here) include fusion of dense features and shifting of line segment positions. Unfortunately, any distorted illumination pattern propagates to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, etc. As a result, the IC performance is degraded or the IC becomes unusable.
FIG. 1C illustrates how optical proximity correction may be employed to modify the reticle design shown in FIG. 1A and thereby better provide the desired illumination pattern. As shown, a corrected reticle 140 includes three base rectangular features 142, 144, and 146 outlined in chromium on a glass plate 150. Various "corrections" have been added to these base features. Some correction takes the form of "serifs" 148a-148f and 149a-149f. Serifs are small appendage-type addition or subtraction regions typically made at corner regions on reticle designs . In the example shown in FIG. 1C, the serifs are square chromium extensions protruding beyond the corners of base rectangles 142, 144, and 146. These features have the intended effect of "sharpening" the corners of the illumination pattern on the wafer surface. In addition to serifs, the reticle 140 includes segments 151a-151d to compensate for feature thinning known to result from optical distortion.
FIG. 1D shows an illumination pattern 160 produced on a wafer surface 160 by radiation passing through the reticle 140. As shown, the illuminated region includes a light region 168 surrounding a set of dark regions 162, 164 and 166 which rather faithfully represent the intended pattern shown in FIG. 1A. Note that the illumination pattern shown in FIG. 1B of an uncorrected reticle has been greatly improved by use of an optical proximity corrected reticle.
The OPC process is generally performed by scanning a digitized version of an IC layout design to identify feature dimensions, interfeature spacing, feature orientation, etc. The scanning process may proceed across the IC layout design in a rasterized fashion to cover the entire pattern. In some IC layout designs, it may also be necessary to conduct raster scans in the two or more directions (e.g., horizontal, vertical, and one or more diagonal directions). In some cases, the OPC computations may include generating a detailed computer model of a reticle image known as a Fast Aerial Image of Mask (FAIM). This image is then itself evaluated to determine where to make reticle corrections.
For more information on OPC scanning techniques, reference may be made to U.S. patent application Ser. No. 08/607,365, filed Feb. 27, 1996 (attorney docket No. P-2693/LSI1P044), entitled "Optical Proximity Correction Method And Apparatus", and assigned to LSI Logic Corporation, the assignee of the present application. That application is hereby incorporated by reference for all purposes.
Not surprisingly, the process of performing OPC on modern IC layout designs having many features can be computationally intensive. In fact, the OPC problem can sometimes be too great for even the most advanced computational resources. Obviously, when FAIM models are used, the computational difficulty increases significantly.
One specific type of optical distortion requiring some form of correction is "reflective notching." This form of distortion arises not from the interaction of light with the reticle pattern itself, but from the interaction of light with structures on the wafer surface. Specifically, light directed onto topographical variations introduced on a wafer surface at certain stages in the IC fabrication process (e.g., field oxide formation) scatters and reflects. As a result, illuminated line patterns crossing over a field oxide/active region interface or other topographically varying surface structure possess notches (reflective notching).
Unfortunately, reflective notching tends to degrade integrated circuit performance. For example, the current carrying characteristics of a polysilicon line will deviate from expectation in these narrow regions, potentially leading to hot spots in the polysilicon line. In some cases, such problems may render the resulting integrated circuit unusable.
To illustrate reflective notching, attention is now drawn to FIG. 2A. FIG. 2A is a top view of a semiconductor wafer section 200 having active regions 202 and 204 surrounded by a field oxide 206. Thus, topographical variations exist at the periphery of diffusion regions 202 and 204. When an image of a polysilicon line 208 is projected onto wafer 200 from a reticle, the locations of intersection between the line image and the topographic variations exhibit reflective notching. This is illustrated by notches 210a-210d at region 202 and 211a-211d at region 204.
FIG. 2B is a cross sectional view of semiconductor wafer 200 of FIG. 2A. The cross sectional view 220 shows a substrate 222 having an n-type diffusion region 228 and a p-type diffusion region 229. As is well known in the art, a field oxide layer is grown between diffused active regions as illustrated by field oxide regions 224a-224c. As shown, field oxide regions 224a-224c may extend higher in the vertical direction than diffusion regions 228 and 229. Therefore, when a polysilicon line 226 is formed over the topographically varying semiconductor surface, notches tend to form at surface transitions 230. In some instances, surface transitions may range between about 1500 .ANG. to about 2000 .ANG.
Reflective notching is further discussed in an article entitled Effects of Wafer Topography on the Formation of Polysilicon Gates, by Robert Socha et al., Department of Electrical Engineering and Computer Science, University of Calif. at Berkeley and Advanced Micro Devices of Sunnyvale, Calif. (SPIE Proceedings, 1995). This article describes a series of studies directed at reducing reflective notching effects on polysilicon. One proposed solution involves the addition of a TiN anti-reflective coating (ARC) layer and the addition of a dye to the photoresist. The ARC layers and dye materials are designed to increase the absorption of light and decrease reflections and scattering that contribute to reflective notching. Although the addition of an ARC layer reduced some reflective notching, the authors warned that adding another layer is very costly and may cause heavy metal contamination.
Another problem associated with photolithography is that associated with depth of focus or depth of field effects of a metallization layer reticle pattern onto a metal surface having topological variations outside the tolerable plane of focus of the projected reticle image. Unlike "reflective notching" which tends to degrade integrated circuit performance of the polysilicon lines, the depth of focus effects upon elevated regions of the metal surface which are sufficiently above the optimal plane of focus of the reticle image tend to degrade reliability of the affected metal lines.
For example, as shown in FIGS. 3 and 4, depth of focus problems typically originate from a lack of local uniformity in the generally planar metal surface 231 of a wafer section 232. FIG. 3 illustrates a top view of a metal surface 231 of semiconductor wafer section 232 having an underlying polysilicon gates 233, 234 surrounded by a field oxide features 235. Similarly, FIG. 4 illustrates a cross sectional view of the semiconductor wafer section 232 of FIG. 3 which shows a substrate 236 having an n-type diffusion region 237 and a p-type diffusion region 237'. Polysilicon gates 233, 234 are further positioned over diffusion regions 237, 237', respectively. A dielectric layer 238 is then deposited atop the gate level, which in turn includes a metal layer 239 overlaying the dielectric layer 238, wherein the elevated portions 240-244 (illustrated in broken lines) are primarily caused by the underlying polysilicon gates 237, 237' and the field oxide features 235. These elevated regions of the metal layer 239, may extend substantially higher in the vertical direction than the plane of focus 245 of the reticle image and the adjacent valley regions 246.
These local topographical variations, however, are primarily caused by the underlying geometry at the gate level 249 (e.g., the polysilicon gate electrodes 233, 234 and the field oxide features 235). More specifically, when the topographical variations extend sufficiently above and below the plane of focus 245 of the metallization reticle pattern, de-focusing occurs with the affected regions. Such focal problems may occur with topographical variations as little as 0.01 .mu.m.
Therefore, when an image 247, 247' of a metal line (FIG. 4) is projected onto a metal surface 231 from a reticle (not shown), the locations of intersection between the line image and any of these elevated portions 240-244 of the metal surface 231 cause depth of focus problems. These unfocused images of the metal lines are exhibited as metal line thinning which results in narrowed regions 248 of the defined metal line image 247, and in narrowed regions 248' of the defined metal line 247'(FIG. 3).
As a consequence, these narrow regions result in an etched metal line which cause "current crowding" therethrough. These areas of increased resistance become even more apparent when large currents are applied which can cause electromigration. Advanced stages of electromigration may result in line failure and ultimately affect reliability. Hence, as the metal line widths become smaller with more advanced technologies, the importance of electromigration issues increases which in turn further increases the importance of controlling metal line width variations.
Further, as shown in FIGS. 4, depth of focus problems may also occur in the metal layer where the projection of the affected metal line 247' does not even vertically intersect the underlying geometry. However, the underlying geometry, for example the polysilicon gate 234, may be sufficiently close to the vertically projected metal line 247' such that the elevated portion 243 at the metal surface 231 still causes focal disparities to induce depth of focus effects.
While conventional OPC techniques are typically only applied to modify the polysilicon layer, since line width control in this area is considered extremely crucial of performance, such techniques are not applied to mitigate the depth of focus effects, and hence electromigration. For instance, these OPC techniques are typically employed to compensate for photolithographic effects for the purposes of reducing transistor leakage whereby the entire polysilicon line is usually adjusted (biased) upwards (increased) in width. Such width increases along the entire line for electromigration improvements may be problematic due to metal capacitance changes, cross talk, forbidden gap problems or the like. Hence, these techniques are not employed in the photolithography of the metallization layers to address the electromigration problems caused by adjacent lines.
In view of the problems discussed above, what is needed is a computationally economical method of performing OPC to correct for reflective notching and other optical distortions in a reticle images.